In the field of liquid crystal display devices, recent trend is the widespread use of active matrix liquid crystal display devices in which each pixel has a nonlinear active element (e.g. a thin-film transistor, a field-effect transistor, a diode). This is because such active matrix liquid crystal display devices can attain excellent image quality by reducing unnecessary signal interferences.
Such active matrix liquid crystal display devices prevent deterioration of image quality by performing alternating driving. In the alternating driving, voltages applied to the liquid crystal layer have alternately opposite polarities. This driving method is classified primarily into two types: line inversion driving and dot inversion driving. In the line inversion driving, polarities of the voltages applied to the liquid crystal layer are alternated on scanning lines. In the dot inversion driving, polarities of the voltages applied to the liquid crystal layer are alternated on signal lines. The special frequency can be set higher in the dot inversion driving than in the line inversion driving. Therefore, the dot inversion driving can attain more excellent display quality.
In a liquid crystal device that uses, for example, TFTs (thin-film transistors) as active elements, a TFT substrate and an opposed substrate are provided, and a liquid crystal layer is sandwiched therebetween. On the TFT substrate, a plurality of signal lines and a plurality of scanning lines intersect, and a TFT and a pixel electrode are provided at each intersection. On the opposed substrate, a common electrode is provided. Each TFT is connected to a scanning line via a gate electrode, to a signal line via a source electrode, and to a pixel electrode via a drain electrode.
In such a liquid crystal display device, while a TFT is ON, a current flows from the signal line to the drain, thereby charging a liquid crystal capacitance Clc, which is provided by the pixel electrode, common electrode, and liquid crystal layer. While the TFT is OFF, the voltage applied to the liquid crystal capacitance Clc is retained.
Conventionally, the pixel electrode is located in a compartment formed by scanning lines and signal lines. However, according to a recently used arrangement, the aperture ratio is increased by superimposing the pixel electrode on the signal lines and scanning lines. To adopt this arrangement, the pixel electrode is isolated from the signal lines and scanning lines by an interlayer insulating film. FIG. 13(a) illustrates an arrangement in which pixel electrodes 50 are superimposed on signal lines 51. In FIG. 13(a), with respect to arbitrary three pixels A, B, and C, an arrangement of pixel electrodes 50A, 50B, and 50C, and signal lines 51B and 51C are illustrated. In FIG. 13(a), the pixels A, B, and C are arrayed in the lateral direction, which is parallel to the scanning lines. The signal lines 51B and 51C respectively charge the pixels B and C (to be more accurate, the signal lines 51B and 51C charge the liquid crystal capacitance Clc). The signal line 51B is connected to the pixel electrode 50B via the TFT 52B. The signal line 51C is connected to the pixel electrode 50C via the TFT 52C. In the following description, alphabets (A, B, C, etc.) are omitted from reference numerals, in the cases where it is not particularly required to discriminate pixels.
The signal line 51B is provided in such a manner as to bridge the adjacent pixel electrodes 50A and 50B, thereby filling the gap therebetween. Likewise, the signal line 51C is provided in such a manner as to bridge the adjacent pixel electrodes 50B and 50C, thereby filling the gap therebetween.
With this arrangement, in which the pixel electrodes 50 are superimposed on the signal lines 51 and/or on the scanning lines, capacitances are provided by the signal lines 51 and/or the scanning lines, the pixel electrodes 50, and superimposed portions of the insulating layer. Among the capacitances, particularly of note are capacitances Csd. The capacitances Csd are provided by the pixel electrode 50, the signal lines 51, and the interlayer insulating film provided therebetween. During an OFF-period of a TFT, there is always a signal flowing on a signal line 51 corresponding to the TFT. The signal is a write signal to be supplied to a pixel electrode 50 corresponding to a scanning line other than the scanning line corresponding to the TFT. Therefore, the drain voltage fluctuates through the capacitances Csd. Accordingly, the voltage to be retained in the liquid crystal capacitance Clc also fluctuates. In the case of color display, change of hue is caused if the voltage to be retained in the liquid crystal capacitance Clc fluctuates.
The dot inversion driving, in which the polarities are alternated on the signal lines, can effectively reduce the fluctuation of the drain voltage occurring through the capacitance Csd. In the dot inversion driving, the polarity of the signal (voltage) applied to a signal line 51 is inverted at each horizontal scanning period, which is determined appropriately. Therefore, there is a 180-degree difference between the phases of adjacent signal lines 51. As a result, although the influences on the drain potential cannot be eliminated, it is possible to cause the influences on the drain potential to be directly opposite, so that the influences cancel out each other.
The fluctuation ΔVdr of the drain potential in each pixel is represented by the following formula:ΔVdr=Csd1/Cpix×ΔVs1+Csd2/Cpix×ΔVs2where Csd1 is a capacitance provided by a signal line 51 for charging the drain, a pixel electrode 50, and an interlayer insulating film; Csd2 is a capacitance provided by an adjacent signal line 51, the pixel electrode, and the interlayer insulating film; Cpix is a sum of capacitances associated with the drain; ΔVs1 is a value of voltage fluctuation obtained by subtracting a pre-change potential of the signal line 51 for charging the drain from a post-change potential of the signal line 51 for charging the drain; and ΔVs2 is a value of voltage fluctuation obtained by subtracting a pre-change potential of a signal line 51 for charging an adjacent pixel from a post-change potential of the signal line 51 for charging the adjacent pixel.
According to FIG. 13(a), the formula can be explained as follows: Csd1 is a capacitance provided by the signal line 51B (which charges the drain of the TFT 52B), the pixel electrode 50B, and the interlayer insulating film; Csd2 is a capacitance provided by the adjacent signal line 51C, the pixel electrode 50B, and the interlayer insulating film; Cpix is a sum of capacitances associated with the drain; ΔVsl is a value of voltage fluctuation obtained by subtracting a pre-change potential of the signal line 51B (which charges the drain of the TFT 52B) from a post-change potential of the signal line 51B (which charges the drain of the TFT 52B); and ΔVs2 is a value of voltage fluctuation obtained by subtracting a pre-change potential of the adjacent signal line 51C from a post-change potential of the adjacent signal line 51C.
FIG. 15 is a schematic diagram illustrating the fluctuation of the drain potential of the TFT 52B. The fluctuation is caused by signals respectively flowing on the signal lines 51B and 51C. As shown in FIG. 15, if ΔVs1 is a positive value, ΔVs2 is a negative value, and vice versa. If the values of Csd1 and Csd2 are equal, and absolute values of ΔVs1 and ΔVs2 are equal, the influences on the drain potential are completely cancelled out.
Therefore, in a conventional arrangement, the signal lines 51B and 51C are superimposed on the pixel electrode 50B so that the superimposed areas are identical on the signal line 51B and on the signal line 51C, as shown in FIG. 13(a) and FIG. 14(a) (cross-sectional view of FIG. 13(a)).
However, even if the two signal lines 51B and 51C are respectively provided at both edges of the pixel electrode 50B so that the superimposed areas are identical on the two signal lines 51B and 51C, the superimposed areas change if the pixel electrode 50B is shifted with respect to the two signal lines 51B and 51C, as shown in FIG. 13(b) and FIG. 14(b) (cross-sectional view of FIG. 13(b). Therefore, the values of Csd1 and Csd2, which are respectively formed at both edges of the pixel electrode 50B, are different. If the values of Csd1 and Csd2 are different, the influences on the drain potential are different. As a result, ΔVdr differs between a shifted region and a normal region. Therefore, effective values are different between the shifted region and the normal region. The difference is observed as uneven display.
In order to reduce the change of the values of Csd1 and Csd2 caused by the shift of the pixel electrode with respect to the signal lines, the following arrangement (ladder structure) is proposed. In FIG. 13(a), the signal line 51B is provided so as to bridge the adjacent signal lines 50A and SOB. On the other hand, according to the ladder structure, two branch signal lines 51B-1 and 51B-2 are provided, as shown in FIG. 16(a) and FIG. 17(a) (cross-sectional view of FIG. 16(a)). The branch signal line 51B-1 is located within the region of the pixel electrode 50A, and the branch signal line 51B-2 is located within the region of the pixel electrode 50B.
FIG. 18 is a plan view illustrating a TFT substrate that adopts the ladder structure. In FIG. 18, the plurality of lines extending in the lateral direction are scanning lines 53. The plurality of lines intersecting the scanning lines 53 are signal lines 51. Indicated by virtual lines, pixel electrodes 50 are provided so as to be superimposed at peripheral portions on the scanning lines 53 and signal lines 51. On a light transmitting substrate (not shown) made of such material as glass, the scanning lines 53, the signal lines 51, and the pixel electrodes 50 are provided in this order. Between an electrode layer including the scanning lines 53 and an electrode layer including the signal lines 51, a gate insulating film (not shown) is provided. Between the electrode layer including the signal lines 51 and an electrode layer including the pixel electrodes 50, an interlayer insulating film (not shown) is provided.
Here, attention is focused on the pixel B. The signal line 51B is divided into the branch signal lines 51B-1 and 51B-2, except the portion at which the TFT 52B (hatching part) is located. The branch signal lines 51B-1 and 51B-2 are provided within the regions of the two adjacent pixel electrodes 50A and 50B, respectively. In FIG. 18, the reference numeral 55 indicates a Cs wire, and the reference numeral 54 indicates a Cs electrode. The Cs wire and the Cs electrode provide a storage capacitance. The Cs wire 55 is provided in the same electrode layer with the scanning lines 53, and the Cs electrode 54 is provided in the same electrode layer with the signal lines 51.
According to this structure, if there is an enough distance between two branch signal lines 51-1 and 51-2, the superimposed areas of the pixel electrode 50B and the branch signal lines 51B-2 and 51C-1, which are respectively provided at both edges of the pixel electrode 50B, do not change (see FIG. 16(b) and FIG. 17(b)), even if the pixel electrode 50 is shifted with respect to the signal lines 51. Thus, the difference between the values of Csd1 and Csd2 can be reduced. As a result, it is possible to set a wide process margin (see, for example, Japanese Publication for Unexamined Patent Application, Tokukaihei No. 09-152625 (publication date: Jun. 10, 1997; corresponding to U.S. Pat. No. 6,052,162, No. 5,953,084, No. 6,097,452, No. 6,195,138B1, and No. 6,433,851B2), and Japanese Publication for Unexamined Patent Application, Tokukaihei No. 10-253988 (publication date: Sep. 25, 1998)).
The explanation above uses TFTs as one example of active elements, the influences of parasitic capacitances formed by the pixel electrode and the signal lines are described as a fluctuation of potential of the drain (drain terminal). The same holds true with other active elements, such as field-effect transistors and diodes. That is, the potential of the terminal connected to the pixel electrode fluctuates due to the influences of the parasitic capacitances.
In general, a color-display liquid crystal display device has color filters of three primary colors (red, blue, and green). The color filters of three primary colors constitute a block, and the blocks are arranged in a mosaic-like shape or in strips. Other than such a liquid crystal display device having color filters of odd-number cycle, there is a liquid crystal display device having color filters of even-number cycle, in which the four kinds of filters (red, blue, green, and, in addition, white) constitute a block, and the blocks are arrayed in matrix. An example of the liquid crystal display device having color filters of even-number cycle is disclosed in Japanese Publication for Unexamined Patent Publication, Tokukaihei 02-118521 (publication date: May 2, 1990). With this arrangement, the use of the white filter increases the overall brightness.
However, the ladder structure is inevitably complex, because a signal line 51 of each pixel is divided into two. Moreover, because the two signal lines 51-1 and 51-2 are provided with respect to each pixel electrode 50, the areas occupied by the signal lines 51 is increased with respect to the areas of apertures. As a result, the aperture ratio decreases.